mir-cpuid 0.5.4

CPU Information

void main()
{
    import std.stdio;
    import cpuid.unified;

    cpuid_init();

    enum fmt = "%14s: %s";

    fmt.writefln("cores", cores);
    fmt.writefln("threads", threads);

    fmt.writefln("data caches", dCache.length);
    fmt.writefln("code caches", iCache.length);
    fmt.writefln("unified caches", uCache.length);

    fmt.writefln("data TLBs", dTlb.length);
    fmt.writefln("code TLBs", iTlb.length);
    fmt.writefln("unified TLBs", uTlb.length);
}

This package also can be used as workaround for core.cpuid Issue 16028.

Documentation

See http://docs.cpuid.dlang.io .

Testing

See all reports.

Run the following command from the project's directory to receive a report about your CPU

dub --single report.d

Please report dub log in a new GitHub issue!

See also output example.

Building a betterC library

dub build --compiler=ldmd2 --build=betterC --build-mode=singleFile --parallel

API Features

• API was split to unified, target specified, and vendor specified parts.
• Complex cache topology (number of cores per cache) is supported. This feature is required by ARM CPUs.
• Translation lookaside buffers are supported. They are used in server and math software, for example cache optimized BLAS requires TLB information.
• Caches and TLBs are split into three types:
• Data
• Instruction (code)
• Unified (data and code)
• _cpuid function is available for x86/x86-64 targets.

Implementation Features

• The library was written completely from scratch.
• Code is clean and simple.
• Unions and mir.bitmanip.bitfields are used instead of bit operations.
• Slim betterC library with extern(C) insterface.

TODO

• [x] Add information about recent features like AVX2, AVX512F.
• [ ] Add information about ARM target and ARM vendors.
• [x] Test a lot of different CPUs.
• [ ] Extend testing infrastructure.